In order to achieve the purpose of saving power, an integrated circuit (IC) design adopting different power modes has been used widely. FIG. 1 is a schematic diagram illustrating a clock tree (or a clock network) in a traditional integrated circuit 100. Referring to FIG. 1, the same integrated circuit (or chip) 100 may be divided into various different function modules such as a micro-processor unit (MPU) function module 110 and a digital signal processor (DSP) function module 120. In a power mode of full speed, based on operations of a control circuit inside (or outside) the integrated circuit 100, the MPU function module 110 and the DSP function module 120 are both operated at a maximum power voltage. For instance, a power voltage VMPU of the MPU function module 110 and a power voltage VDSP of the DSP function module 120 are both 1.0V. In a power mode of one certain operating condition, the power voltage VMPU of the MPU function module 110 is maintained at 1.0V, whereas the power voltage VDSP of the DSP function module 120 may be reduced (e.g., reduced to 0.4V) for saving power. In a power mode of another operating condition, the power voltage VDSP of the DSP function module 120 is maintained at 1.0V, whereas the power voltage VMPU of the MPU function module 110 may be reduced to a low voltage (e.g., reduced to 0.4V). When a power mode of idle is entered, the power voltage VMPU of the MPU function module 110 and the power voltage VDSP of the DSP function module 120 may both be reduced to 0.4V, so as to achieve the purpose of saving power.
At a clock tree synthesis (CTS) stage, a clock tree may be automatically synthesized by an electronic design automation (EDA) software. A common clock tree uses a plurality of clock buffers (e.g., clock buffers 101 to 107 depicted in FIG. 1) to gain a system clock CLK for transferring to the next clock buffer or other components. The system clock CLK may be transferred to each of the components (not illustrated) inside the integrated circuit 100 through said clock tree, and said components may be, for example, registers inside the integrated circuit 100 and/or other components under control of the system clock CLK. Ideally, the system clock CLK may simultaneously reach each of the components inside the integrated circuit 100 through the clock tree. Yet, skew factors such as transferring paths, loadings and so on may generally cause inconsistent times for the system clock CLK to reach each of the components inside the integrated circuit 100 (i.e., a clock latency), and a time difference for the system clock CLK to reach different components is known as a clock skew.
The EDA software is capable of increasing/decreasing an amount of the clock buffers for one specific operating condition to adjust delay times of the clock buffers 101 to 107, and thereby optimizing (minimizing) the clock skew. For example, in the power mode of full speed (in which the power voltages of the MPU function module 110 and the DSP function module 120 are both 1.0V), the clock latencies of the MPU function module 110 and the DSP function module 120 are 0.28 ns and 0.23 ns respectively, and thus the clock skew at the time is 0.05 ns. However, because the power voltage has a great influence on a clock delay of the clock buffer, different power modes may generate innegligible time differences for the system clock to reach each function module. Table 1 illustrates the clock skews for the MPU function module 110 and the DSP function module 120 depicted in FIG. 1 respectively under different power modes. When the power voltage VDSP of the DSP function module 120 is reduced from 1.0V to 0.4V, the clock latency of the DSP function module 120 is increased to 7.00 ns, such that the clock skew between the MPU function module 110 and the DSP function module 120 is correspondingly increased to 7.00−0.28=6.72 ns. When the power voltage VMPU of the MPU function module 110 is reduced from 1.0V to 0.4V, the clock latency of the MPU function module 110 is increased to 9.37 ns, such that the clock skew between the MPU function module 110 and the DSP function module 120 is correspondingly increased to 9.37−0.23=9.14 ns. When the power voltage VMPU of the MPU function module 110 and the power voltage VDSP of the DSP function module 120 are both reduced from 1.0V to 0.4V, the clock latency of the MPU function module 110 is increased to 9.37 ns and the clock latency of the DSP function module 120 is increased to 7.00 ns, such that the clock skew between the MPU function module 110 and the DSP function module 120 is correspondingly increased to 9.37−7.00=2.37 ns. Accordingly, the clock tree depicted in FIG. 1 cannot satisfy limitations from the clock skews for all power modes.
TABLE 1the clock skews for the MPU function module 110 and the DSP functionmodule 120 depicted in FIG. 1 respectively under different power modesare illustrated.MPU functionDSP functionmodule 110module 120PowerPowerClockPower ModeVoltageClock LatencyVoltageLatencyClock Skew11.0 V0.28 ns1.0 V0.23 ns0.05 ns21.0 V0.28 ns0.4 V7.00 ns6.72 ns30.4 V9.37 ns1.0 V0.23 ns9.14 ns40.4 V9.37 ns0.4 V7.00 ns2.37 ns
Generally, a clock synchronization for multiple power modes design may be classified into the following methods. (1) An asynchronous design; (2) utilization of an adjustable delay buffer (ADB); and (3) utilization of a delay locked loop (DLL). In case the design adopts the asynchronous design, a handshake protocol may be developed, which increases difficulties in both system design and authentication. Moreover, additional synchronous circuits may be further required for data synchronizing. In case the adjustable delay buffer or the delay locked loop is utilized, clock signals may be returned from a plurality of ends in the clock tree for phase comparison. Therefore, additional circuit designs and placements for the adjustable delay buffer or the delay locked loop are required, which consume an innegligible cost in terms of area. Furthermore, the adjustable delay buffer or the delay locked loop also requires additional reference clocks, and a choice of the reference clocks may affect performance for the design of the clock synchronization.